AK4527B Datasheet, PDF (6/33 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC

ASAHI KASEI
[AK4527B]
No. Pin Name
23 LOUT3
24 ROUT3
25 LOUT2
26 ROUT2
27 LOUT1
28 ROUT1
29 LIN-
30 LIN+
31 RIN-
32 RIN+
33 DZF2
OVF
34 VCOM
35 VREFH
36 AVDD
37 AVSS
38 DZF1
39 MCLK
40 P/S
41 DIF0
CSN
42 DIF1
SCL/CCLK
43 LOOP0
SDA/CDTI
44 LOOP1
I/O
Function
O DAC3 Lch Analog Output Pin
O DAC3 Rch Analog Output Pin
O DAC2 Lch Analog Output Pin
O DAC2 Rch Analog Output Pin
O DAC1 Lch Analog Output Pin
O DAC1 Rch Analog Output Pin
I Lch Analog Negative Input Pin
I Lch Analog Positive Input Pin
I Rch Analog Negative Input Pin
I Rch Analog Positive Input Pin
O Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
O Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch is overflows.
O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
I Positive Voltage Reference Input Pin, AVDD
- Analog Power Supply Pin, 4.5V∼5.5V
- Analog Ground Pin, 0V
O Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
I Master Clock Input Pin
I Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
I Audio Data Interface Format 0 Pin in parallel control mode
I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I²C bus control mode
I Audio Data Interface Format 1 Pin in parallel control mode
I Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I²C Bus)
I Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 3 DACs.
I/O Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I²C Bus)
I Loopback Mode 1 Pin
(Note 1)
Enables all 3 DAC channels to be input from SDTI1.
Notes: 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM2-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All input pins should not be left floating.
MS0056-E-00
-6-
2000/10