AK4527B Datasheet, PDF (11/33 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC

ASAHI KASEI
[AK4527B]
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 21)
(Note 22)
Symbol
min
typ
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
0.025*1/fs
50
50
fSCL
-
tBUF
4.7
tHD:STA
4.0
tLOW
4.7
tHIGH
4.0
tSU:STA
4.7
tHD:DAT
0
tSU:DAT
0.25
tR
-
tF
-
tSU:STO
4.0
tSP
0
tPD
tPDV
150
522
Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
21. The AK4527B can be reset by bringing PDN “L” to “H” upon power-up.
22. These cycles are the number of LRCK rising from PDN rising.
23. I²C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
20
ns
20
ns
20
ns
100 kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0 µs
0.3 µs
-
µs
50
ns
ns
1/fs
Purchase of Asahi Kasei Microsystems Co., Ltd I²C components conveys a license under the Philips
I²C patent to use the components in the I²C system, provided the system conform to the I²C
specifications defined by Philips.
MS0056-E-00
- 11 -
2000/10