AK4527B Datasheet, PDF (14/33 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC

ASAHI KASEI
[AK4527B]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4527B, are MCLK, LRCK and BICK. There are two methods to
set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS (Table 1). The
frequency of MCLK at each sampling speed is set automatically. (Table 2, 3). In Auto Setting Mode (ACKS = “1”), as
MCLK frequency is detected automatically (Table 4), and the internal master clock becomes the appropriate frequency
(Table 5), it is not necessary to set DFS.
MCLK should be synchronized with LRCK but the phase is not critical. External clocks (MCLK, BICK) should always be
present whenever the AK4527B is in normal operation mode (PDN = “H”). If these clocks are not provided, the
AK4527B may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks
are not present, the AK4527B should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After
exiting reset at power-up etc., the AK4527B is in the power-down mode until MCLK and LRCK are input.
DFS
Sampling Speed (fs)
0
Normal Speed Mode
32kHz~48kHz Default
1
Double Speed Mode
64kHz~96kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK (MHz)
192fs
16.9344
18.4320
256fs
22.5792
24.5760
BICK (MHz)
64fs
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At double speed mode(DFS = “1”), 128fs and 192fs are not available for ADC.)
MCLK
512fs
256fs
Sampling Speed
Normal
Double
Table 4. Sampling Speed (Auto Setting Mode)
MS0056-E-00
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