AK4527B Datasheet, PDF (24/33 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC

ASAHI KASEI
[AK4527B]
n Register Definitions
Addr Register Name
00H Control 1
default
D7 D6
D5
D4
D3
0
0
0
0
DIF1
0
0
0
0
1
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin if P/S = “L”.
DIF1-0: Audio Data Interface Modes (see table 7.)
Initial: “10”, mode 2
D2
DIF0
0
D1
D0
0 SMUTE
0
0
Addr Register Name
01H Control 2
default
D7 D6
D5
D4
D3
D2
D1
D0
0
0 LOOP1 LOOP0 SDOS DFS ACKS 0
0
0
0
0
0
0
0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are
ignored. When this bit is “0”, DFS sets the sampling speed mode.
DFS: Sampling speed mode (see table 1.)
0: Normal speed
1: Double speed
Register bit of DFS is ORed with DFS pin if P/S = “L”. The setting of DFS are ignored at ACKS bit “1”.
SDOS: SDTO source select
0: ADC
1: DAUX
Register bit of SDOS is ORed with SDOS pin if P/S = “L”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3
RIN → ROUT1, ROUT2, ROUT3
The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this
mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode
becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
10: SDTI1(L) → SDTI2(L), SDTI3(L)
SDTI1(R) → SDTI2(R), SDTI3(R)
In this mode the input DAC data to SDTI2-3 is ignored.
11: N/A
Register bit of LOOP1 is ORed with LOOP1 pin if P/S = “L”.
MS0056-E-00
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