AK2346A Datasheet, PDF (6/37 Pages) Asahi Kasei Microsystems – Two-way Radio Audio Processor

ASAHI KASEI
[AK2346A]
Package
Pin No Name
10 RXIN
11 RXINO
12 FILTERO
13 RXOUT
14 AGNDIN
15 AGND
16 EXTIN1
17 EXTINO
18 VSS2
19 TXIN
20 TXINO
21 EXTIN2
22 MOD
Signal
Type
AI
AO
AO
AO
AI
AO
AI
AO
PWR
AI
AO
AI
AO
Conditions
at power
down
Z
Z
Z
Z
*1)
*1)
Z
Z
-
Z
Z
Z
Z
Function
Demodulated audio signal input pin.
This is the inverting input of RXA1. It composes a pre-filter with
external resistor and capacitor.
RXA1 feedback output pin.
RXLPF circuit and TX/RX_HPF circuit output pin. LPF output
pin. This is a monitor pin for tone signal. 57.6kHz
sampling-clock is included, so please eliminate this signal
component by LPF externally.
Receive audio signal output pin.
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level.
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
TXA2 feedback input pin.
This is the inverting input pin for TXA2. It composes a
microphone amplifier with an external resistor and capacitor.
TXA2 feedback output pin.
VSS power supply pin.
Normally supply 0V to this pin.
Transmit audio signal input pin.
This is the inverting input pin for TXA1. It composes a
microphone amplifier with an external resistor and capacitor.
TXA1 feedback output pin.
External input pin.
This pin is available for external tone signal.
The modulated transmit signal output pin.
23
24
Note
RSTN
DI
Z
Reset pin.
MSK signal MSK signal transmitted and received data input and
output pin.
In transmission, AK2346A reads data synchronized with the
rising edge of MSKCLK.
This pin outputs 2 kinds of information according to the
setting of FSL register.
This pin puts out two types of signal that depends on the status
MSKDATA DB
Z
of register named FSL.
In case FSL equal “1”, it is received flag mode (RDF). So the pin
puts out low level after 8 bits of MSK receive signal have been
written to the internal register.
In case FSL equal “0”, it is frame detection mode (FD). So the
low pulse is put out after a frame pattern is detected.
When MSKSW[1:0] register is set to “1/0”, RDATA signal is put
out.
A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bidirectional, Z: High-Z, L: Low
*1) AGND level
*2) When XIN pin is set to low level, XOUT pin goes to high level.
MS1289-E-02
-6-
2012/06