AK2346A Datasheet, PDF (5/37 Pages) Asahi Kasei Microsystems – Two-way Radio Audio Processor

ASAHI KASEI
[AK2346A]
Block
MSK BPF
MSK Demodulator
MSK Modulator
AGND
OSC
DIV
Control
Register
Description
The Band-pass filter to eliminate the low and high frequency component for received MSK
signal.
The circuit to reproduce the 1200/2400bit/s receive clock and data from MSK signal at
RXIN pin.
The circuit to generate a MSK signal according to the received digital data from
MSKDATA pin.
The circuit to generate the reference voltage (1/2VDD) for internal analog signal.
The circuit to oscillate the 14.7456MHz reference clock with an external crystal oscillator
and resistor and capacitors.
The circuit to generate 1/2,1/3 or 1/4 frequency-divided output When a signal whose
frequency is twice, three times, or four times higher than 3.6864MHz is input from the
outside, this circuit divides the signal frequency by two, three, or four.
MCKSL[1:0] register is used to set this block.
The control register controls the status of internal switches and digitally controlled
amplifiers of IC by serial data that consists of 4 address bits and 8 data bits.
The data buffer stores 8 bits of the MSK received data to smooth the signal interface with
microprocessor.
At the start up, RSTN-pin is used for system reset. SRST register is used for software
reset. (Refer to the control register map)
6. Pin/Function
Package
Pin No Name
1 MSKCLK
2 DIO
3 SCLK
4 DIR
5 XOUT
6 XIN
7 DVDD
8 VSS1
9 AVDD
Signal
Type
DO
DB
DI
Conditions
at power
down
H
Z
Z
Function
Clock input and output pin for MSK signal.
Serial data input and output pin.
Input for register setting data and output for MSK receive data.
Clock input pin for serial data I/O.
DI
Z
Serial data I/O control pin.
DO
DI
PWR
PWR
PWR
*2)
Crystal oscillator connecting input pin.
Crystal oscillator connecting input and output pin.
To connect a 14.7456MHz crystal oscillator between this pin
*2)
and XOUT pin generates the reference clock internally.
In case of externally supplied clock operation, connect to this
pin. For more information, please refer to external application
circuits.
Digital VDD power supply pin.
-
Normally connect to 2.6V to 5.5V power-supply. Also this pin
must be decoupled to VSS pin by 0.1uF capacitor mounted
close to the device pins.
-
VSS power supply pin.
Normally supply 0V to this pin.
Analog VDD power supply pin.
Normally connect to 2.6V to 5.5V power-supply. Also this pin
-
must be decoupled to VSS pin by 0.1uF capacitor mounted
close to the device pins.
Applied voltage must be DVDD ≤ AVDD
MS1289-E-02
-5-
2012/06