AK2346A Datasheet, PDF (31/37 Pages) Asahi Kasei Microsystems – Two-way Radio Audio Processor

ASAHI KASEI
[AK2346A]
2) MSK Demodulator control flow
2.1) When frame detection is used
MSK data receiver, Demodulator interfaces with RXIN, MSKDATA, SCLK, DIO and DIR pins and
also FSL, RXSW and FCLN registers as below.
FCLN=0
FSL=0
N
MSKDATA “Low”
Y
FCLN=1 (automatically)
RXSW=0
FSL=1
N
MSKDATA “Low”
Y
Reading receive data
N
Have all receive data
been read out?
Y
FCLN=0
: Setting flame detect (FD) enable
: Setting for FD signal put out from
MSKDATA pin.
: Synchronized frame pattern
detect or not ?
: FD is disable automatically
: Receive audio mute
: Setting for received flag (RDF) signal
put out from MSKDATA pin.
: 8 bit data received or not ?
: Having read 8bit data, MSKDATA pin
puts out high level.
: Waiting for the next synchronized
flame.
(1) Set MSKSW1=0 and MSKSW0=0 for flame detect mode.
(2) Setting FCLN=0 and FSL=0 and also SCLK pin sets high level and DIR pin sets low level,
MSKDATA pin puts out high level and wait for synchronized frame.
(Point A)
(3) After a synchronized frame is detected, MSKDATA pin works as frame detect (FD) mode.
FD goes to low level during the period of time “T”, then FCLN is sets to “1” automatically.
(Point B, C)
MS1289-E-02
2012/06
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