AK2303LV Datasheet, PDF (6/41 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for PBX Analog Line Card

ASAHI KASEI
Pin# Name
1 TEST
2 VFTN1
3 GST1
4 GSR1
5 VFR1
6 VR1
7 ALAWN
8 AVDD
9 DVDD
10 FS
11 BCLK
12 DX
13 DR
14 MUTE1
15 MUTE0
16 SCLK
17 DATA
18 CSN
19 LPC
[AK2303LV]
PIN FUNCTION
I/O
Function
I TEST MODE setting (Please tie to AVSS)
0: Normal mode 1: Test mode
I Negative analog input of the transmit OPamp(AMPT1) for channel 1.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST1.
O Output of the transmit OPamp(AMPT1) for channel 1.
O Output of the receive OPamp(AMPR1) for channel 1.
I Negative analog input of the receive OPamp(AMTR1) for channel 1.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR1.
O Analog Output equivalent to the received PCM data for channel 1.
I A-law/u-law Select
0：A-law 1：u-law
- Positive supply voltage for analog circuit.
+3.3V supply.
- Positive supply voltage for digital circuit.
+3.3V supply.
I Frame sync input.
FS must be 8kHz clock which is synchronized with BCLK.
I Bit clock of PCM data interface.
This clock is input for the internal PLL which gerenates the internal system clocks.
This clock defines the input/output data rate of DX and DR.
The frequency of BCLK should be 2.048MHz or 4.096MHz set via CPU register..
O Serial output of PCM data.
The channel 1 data is output following the channel 0 data. The PCM data rate is
synchronized with BCLK. This output remains in the high impedance state except for the
period of transmitting PCM data.
I Serial input of PCM data.
The channel 1 data is received following the channel 0 data. The PCM data rate is
synchronized with BCLK.
I CH1 mute setting
0：mute 1：normal operation
I CH0 mute setting
0：mute 1：normal operation
I Clock input of serial interface.
I/O Data input of serial interface.
I Read and write enable of serial interface.
O Pin for PLL loop filter.
External capacitance(Min 0.22uF) should be connected between this pin and AVSS.
2303-E-00
6
2001/09