AK2303LV Datasheet, PDF (32/41 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for PBX Analog Line Card

ASAHI KASEI
[AK2303LV]
PCM INTERFACE ( Long Frame, Short Frame, GCI )
Unless otherwise noted, the specification applies for TA = -40 to +85^oC, VDD = 5V±5%/3V±0.3V,VSS = 0V and
FS0= 8kHz. All timing parameters are measured at VOH = 0.8VDD and VOL =0.4V.
Parameter
Symbol Min Typ Max Units Ref Fig
FS Frequency
1/t_PF
-
8
- kHz
BCLK Frequency
1/t_PB 2048
4096 kHz
BCLK Pulse Width High
t_WBH
80
ns
BCLK Pulse Width Low
t_WBL
80
ns
Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1)
Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1)
Hold Time: BCLK Low to FS High
t_R
t_F
t_HBF
40
40 ns
Fig1
40 ns Fig2
Fig3
ns
Setup Time: FS High to BCLK Low
t_SFB
70
ns
Setup Time: DR to BCLK Low
t_SDB
40
ns
Hold Time: BCLK Low to DR
t_HBD
40
ns
Delay Time: BCLK High to DX valid
Note1) t_DBD
60 ns
Long Frame
Hold Time: 2^nd period of BCLK Low to FS Low
t_HBFL
40
Delay Time: FS or BCLK High, whichever is later,to DX valid
Note1)
t_DZFL
Delay Time: BCLK Low to DX High-Z
Note1) t_DZCL 10
FS Pulse Width Low
t_WFSL
1
Short Frame
ns
60 ns
Fig1
60 ns
BCL
K
Hold Time: BCLK Low to FS Low
Setup Time: FS Low to BCLK Low
Delay Time: BCLK Low to DX High-Z
GCI
Note1)
t_HBFS
40
t_SFBS
40
t_DZCS
10
ns
ns Fig2
60 ns
BCLK Frequency
1/t_PBG 2048
Delay Time: Second BCLK Low to DX High-Z
t_DZCG 10
Setup Time: DR to Second BCLK High
t_SDBG 40
Hold Time: Second BCLK High to DR
t_HBDG 40
Note1) Measured with 150pF Load capacitance and driving two LSTTLs
4096 kHz
60 ns
Fig3
ns
ns
2303-E-00
32
2001/09