AK2303LV Datasheet, PDF (19/41 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for PBX Analog Line Card

ASAHI KASEI
[AK2303LV]
SERIAL INTERFACE
The internal registers can be read/written with SCLK, DATA, and CSN pins.
1word consists of 16bits. The first 4bits are the instruction code which specifies read/write.
The following 3bits specify the address. The rest of 8bits are for setting registers.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
I3 I2 I1 I0 A2 A1 A0 * D7 D6 D5 D4 D3 D2 D1 D0
Instruction code
(4bit)
Address
(3bit)
*
*)Dummy bit for adjusting the I/O timing when reading register.
Data for internal registers
(8bit)
INSTRUCTION CODEC
I3
I2
I1
I0
1
1
1
0
1
1
1
1
Other codes
Read/Write
Read
Write
No action
SCLK and WRITE/READ
(1) Input data are loaded into the internal shift register at the rising edge of SCLK.
(2) The rising edge of SCLK is counted after the falling edge of CSN.
(3) When CSN is “L” and more than 16 SCLK pulses:
[WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16^th pulse.
[READ] DATA pin is switched to an input pin at the falling edge of the SCLK 16^th pulse.
CSN and WRITE / READ CANCELLATION
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16^th pulse.
(2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16^th pulse.
SERIAL WRITE / READ (SERIAL ACCESS)
(1) CSN must go up to “H” before the next access in successive access.
(2) When the next access is going to be done , if CSN remains to be “L”, successive access can not be done.
2303-E-00
19
2001/09