AK2303LV Datasheet, PDF (12/41 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for PBX Analog Line Card

ASAHI KASEI
GCI ( General Circuit Interface )
GCI data format and clocking which is used for ISDN application is shown as following.
4.096, 2.048MHz can be used for BCLK. Thus, data rate will be 2.048 or 1.024MHz.
[AK2303LV]
Timing of the interface
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 16 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy one time slot
for channel 0 and channel 1, as is indicated in following.
Frame Sync signal (FS)
8kHz reference signal. This signal indicates the timing and the frame position of 8kHz GCI. High level duration of the FS is 1
clock period of BCLK.
Bit Clock (BCLK)
BCLK defines the GCI data rate. All the internal clock of the LSI is generated based on this BCLK signal. The data rate of
GCI is half of BCLK. BCLK can be used either 4.096MHz or 2.048MHz.
Position of the Ch0,Ch1 GCI data in the DX/DR data flow
B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register
as same way as PCM interface. Time-slot also can be assigned by same way as PCM format.
Channel selection
CH0,1selection(Address:100 Bit:6)
SEL2B
CH0
0
B1
CH1
B2
1
B2
B1
Remarks
Default
On Reset
Analog Interface
Channe0
Channel 1
PCM Interface
B1 B2
SEL2B
Time slot Assignment
B1, B2 Time-slot selection (Address:101 Bit:4~0)
TS[4:0] Time slot
B1
B2
00000
0
The first half of 8bit The latter half of
in Time-slot#0
8bit in Time-slot#0
00001 to
01110
XX
The first half of 8bit The latter half of
in Time-slot#XX 8bit in Time-slot#XX
01111
15
The first half of 8bit The latter half of
in Time-slot#15 8bit in Time-slot#15
Remarks
Default
On Reset
2303-E-00
12
2001/09