AK5552VN_16 Datasheet, PDF (59/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit ADC

[AK5552]
SDA
SCL
S
start condition
P
stop condition
Figure 69. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
acknowledge
8
9
Figure 70. Acknowledge on the I²C-Bus
clock pulse for
acknowledgement
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 71. Bit Transfer on the I²C-Bus
015099871-E-00
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2016/03