AK5552VN_16 Datasheet, PDF (44/68 Pages) Asahi Kasei Microsystems – 2-Channel Differential 32-bit ADC

[AK5552]
LRCK (Master)
512 BICK
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23
#8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMIN (I)
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0
23
(#7 SDTO1)
#7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 51. Mode 41/45 Timing (TDM512 mode, I²S Compatible, 24-bit)
LRCK (Master)
512 BICK
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30
#8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMIN (I)
31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 0 1 31 30 1 0 31 30 0 1 31 30 1 0
31 30
(#7 SDTO1)
#7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 52. Mode 42/46 Timing (TDM512 mode, MSB Justified, 32-bit)
LRCK (Master)
512 BICK
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31
#8 Data 1 #8 Data 2 #7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
TDMIN (I)
31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 0 1 31 30 1 0 31 30 0 1 31 30 1 0
31
(#7 SDTO1)
#7 Data 1 #7 Data 2 #6 Data 1 #6 Data 2 #5 Data 1 #5 Data 2 #4 Data 1 #4 Data 2 #3 Data 1 #3 Data 2 #2 Data 1 #2 Data 2 #1 Data 1 #1 Data 2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 53. Mode 43/47 Timing (TDM512 mode, I²S Compatible, 32-bit)
Parameter
MCLK “↑” to BICK “↓”
BICK “↓” to MCLK“↑”
Symbol
Min.
Typ.
tMCB
10
tBIM
10
Table 10. TDM Mode Clock Timing
Max
Unit
ns
ns
015099871-E-00
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2016/03