AK8859VN Datasheet, PDF (56/72 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VN]
[9.1.11.] Sub Address 0x0A “PGA1 Control Register (R/W)”
PGA1 gain control setting register.
PGA1 is used for CVBS and Y signals gain processing.
Sub Address: 0x0A
bit 7
bit 6
PGA1_7
PGA1_6
Default Value
0
0
bit 5
PGA1_5
1
bit 4
PGA1_4
1
bit 3
PGA1_3
1
bit 2
PGA1_2
1
Default Value: 0x3C
bit 1
bit 0
PGA1_1 PGA1_0
0
0
PGA1 Control Register Definition
Register
Bit _Name
bit 0 PGA1_0
~
~
PGA1 Gain Set
bit 7 PGA1_7
R/W Definition
PGA1 gain setting.
R/W _{PGA gain is set by follows equation.}
[9.1.12.] Sub Address 0x0B “PGA2 Control Register (R/W)”
PGA2 gain control setting register.
PGA2 is used for C signal gain processing.
Sub Address: 0x0B
bit 7
bit 6
PGA2_7
PGA2_6
Default Value
0
0
bit 5
PGA2_5
1
bit 4
PGA2_4
1
bit 3
PGA2_3
1
bit 2
PGA2_2
1
Default Value: 0x3C
bit 1
bit 0
PGA2_1 PGA2_0
0
0
PGA2 Control Register Definition
Bit ^Register
Name
bit 0 PGA2_0
~
~
PGA2 Gain Set
bit 7 PGA2_7
R/W Definition
PGA2 gain setting.
R/W
PGA gain is set by follows equation.
PGA gain equation:
Gain(dB) = 20LOG⎜⎛ ^{(2.5 × PGA) + 251.5} ⎟⎞
⎝
401.5
⎠
Default gain setting is 0x3C_(HEX)=0.00dB.
*PGA:PGA1orPGA2 register value_(Dec.)
MS1179-E-00
AKM Confidential
- 56 -
2010/04