AK8859VN Datasheet, PDF (53/72 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VN]
[9.1.7.] Sub Address 0x06 “Output Pin Polarity Set Register (R/W)”
Output pins polarity setting register.
Sub Address: 0x06
bit 7
bit 6
VARP VD_FP
Default Value
0
0
bit 5
HDP
0
bit 4
CLKINV
0
bit 3
Reserved
0
bit 2
Reserved
0
Default Value: 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Output Pin Polarity Set Register Definition
Bit ^Register
R/W
Name
bit 0
~ Reserved Reserved
R/W
bit 3
bit 4 CLKINV CLK Invert Set R/W
bit 5 HDP
HD Pin
R/W
Polarity Set
bit 6 VD_FP
VD_F Pin
R/W
Polarity Set
VAR Pin
bit 7 VARP
R/W
Polarity Set
Definition
Reserved
DTCLK signal output polarity setting.
[0]: Normal output
(write in data at rising edge)
[1]: Data and clock reversed
(write in data at falling edge)
HD signal polarity setting
[0]: Active Low
[1]: Active High
VD_F pin output signal polarity setting
(If VD signal is output)
[0]: Active Low
[1]: Active High
(If Field signal is output)
[0]: Odd-Field Low, Even-Field High
[1]: Even-Field Low, Odd-Field High
VAR pin output signal polarity setting
(If DVALID signal is output)
[0]: Active Low
[1]: Active High
(If Field signal is output)
[0]: Odd-Field Low , Even-Field High
[1]: Even-Field Low , Odd-Field High
(If NSIG signal is output)
[0]: When the input signal is absent the output is High.
[1]: When the input signal is absent the output is Low.
(If LINE signal is output)
[0]: 525L-Low, 625L-High
[1]: 625L-Low, 525L-High
MS1179-E-00
AKM Confidential
- 53 -
2010/04