AK8859VN Datasheet, PDF (3/72 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VN]
[7.22.2] Output timing signal diagram .............................................................................................. 31
[7.23] Digital Pixel interpolator ............................................................................................................. 32
[7.24] Clock generation ......................................................................................................................... 33
[7.24.1.] Line-locked clock mode ...................................................................................................... 33
[7.24.2.] Frame-locked clock mode................................................................................................... 33
[7.24.3.] Fixed-clock mode................................................................................................................. 33
[7.24.4.] Auto transition mode........................................................................................................... 33
[7.25.] PGA (Programmable Gain Amp) ............................................................................................... 33
[7.26.] AGC (Auto Gain Control) ........................................................................................................... 34
[7.27.] ACC (Auto Color Control) .......................................................................................................... 35
[7.28.] Sharpness adjustment ............................................................................................................... 35
[7.29.] Color Killer .................................................................................................................................. 35
[7.30.] Image quality adjustment .......................................................................................................... 36
[7.30.1.] Contrast adjustment ............................................................................................................ 36
[7.30.2.] Brightness adjustment ........................................................................................................ 36
[7.30.3.] Color saturation adjustment............................................................................................... 37
[7.30.4.] HUE adjustment ................................................................................................................... 37
[7.31.] VBI information decoding.......................................................................................................... 38
[7.32.] Internal status indicator............................................................................................................. 39
[7.32.1.] Input signal indicator........................................................................................................... 39
[7.32.2.] Status of VLOCK mechanism ............................................................................................. 39
[7.32.3.] Interlace signal indicator..................................................................................................... 39
[7.32.4.] Color killer operational........................................................................................................ 39
[7.32.5.] Clock mode........................................................................................................................... 39
[7.32.6.] Luminance decode overflow .............................................................................................. 39
[7.32.7.] Color decode overflow ........................................................................................................ 40
[7.32.8.] AGC status............................................................................................................................ 40
[7.33.] Macrovision signal detection .................................................................................................... 40
[7.34.] Auto detection result of input video signal ............................................................................. 41
[8.] Device control interface ..................................................................................................................... 42
[8.1.] I²C bus SLAVE Address ............................................................................................................... 42
[8.2.] I²C control sequence .................................................................................................................... 42
[8.2.1.] Write sequence ...................................................................................................................... 42
[8.2.2.] Read sequence....................................................................................................................... 42
[8.2.3.] I²C General Call ...................................................................................................................... 42
[9.] Register definitions............................................................................................................................. 44
[9.1.] Register setting overview ............................................................................................................ 46
[9.1.1.] Sub Address 0x00 “Input Channel Select Register (R/W)”................................................ 46
[9.1.2.] Sub Address 0x01 “Clamp Control Register (R/W)” .......................................................... 47
[9.1.3.] Sub Address 0x02 “Input Video Standard Register (R/W)” ............................................... 48
[9.1.4.] Sub Address 0x03 “NDMODE Register (R/W)” ................................................................... 49
[9.1.5.] Sub Address 0x04 “Output Format Register (R/W)” .......................................................... 50
[9.1.6.] Sub Address 0x05 “Output Pin Control Register (R/W)” ................................................... 52
[9.1.7.] Sub Address 0x06 “Output Pin Polarity Set Register (R/W)” ............................................ 53
[9.1.8.] Sub Address 0x07 “Control 0 Register (R/W)” ................................................................... 54
[9.1.9.] Sub Address 0x08 “Control 1 Register (R/W)” ................................................................... 55
[9.1.10.] Sub Address 0x09 “Reserved Register (R/W)” ................................................................. 55
[9.1.11.] Sub Address 0x0A “PGA1 Control Register (R/W)” ......................................................... 56
[9.1.12.] Sub Address 0x0B “PGA2 Control Register (R/W)” ......................................................... 56
[9.1.13.] Sub Address 0x0C “AGC and Color Control Register (R/W)”......................................... 57
[9.1.14.] Sub Address 0x0D “Contrast Control Register (R/W)” .................................................... 58
MS1179-E-00
AKM Confidential
-3-
2010/04