AK8859VN Datasheet, PDF (27/72 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VN]
[7.15.] Output pin polarity
The output signals from each digital output pin can be inverted via register.
Setting for output pin polarity
Name
Pin name
HDP
HD
VD_FP
VD_F
VARP
VAR
Output signal
HD
VD
Field
DVALID
Field
NSIG
LINE
Setting value
[0]
Active Low
Active Low
Low: Odd-Field
High: Even-Field
Active Low
Low: Odd-Field
High: Even-Field
High: Signal absent
Low: 525Line
High: 625Line
Sub Address: 0x06 [7:5]
[1]
Active High
Active High
Low: Even-Field
High: Odd-Field
Active High
Low: Even-Field
High: Odd-Field
Low: Signal absent
Low: 625Line
High: 525Line
In addition, it is possible to invert the output signal from the DTCLK pin.
Setting for polarity of DTCLK signal output
Name Definition
[0]: Normal output (write in data at rising edge)
CLKINV _{[1]: Phase of data and clock is invert (write in data at falling edge)}
Sub Address: 0x06 [4]
[7.16.] Phase correction
In PAL-B, D, G, H, I, N, Nc, 60, and M decoding, the AK8859VN performs phase correction for each line.
With this function ON, color averaging is performed for each line. In the adaptive phase correction mode,
interline phase correlation is sampled and color averaging is performed for correlated samples.
Interline color averaging is also performed in NTSC-M and J decoding.
No phase correction or color averaging is performed in SECAM decoding.
Settings for phase correction
Name
Definition
DPAL0
~
DPAL1
[ DPAL1 : DPAL0 ]
[00]: Adaptive phase correction mode
[01]: Phase correction ON
[10]: Phase correction OFF
[11]: Reserved
Sub Address: 0x07 [1:0]
MS1179-E-00
AKM Confidential
- 27 -
2010/04