AK8859VN Datasheet, PDF (33/72 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8859VN]
[7.24] Clock generation
The AK8859VN operates in the following three clock modes:
[7.24.1.] Line-locked clock mode
The “line-locked clock” is generated by PLL using horizontal sync signal within the input signal. If no input
signal is present, the AK8859VN will switch from this mode to fixed-clock mode.
[7.24.2.] Frame-locked clock mode
The “frame-locked clock” is generated by PLL using vertical sync signal within the input signal. If no signal
is present, the AK8859VN will switch from this mode to fixed-clock mode.
[7.24.3.] Fixed-clock mode
No PLL control is applied in this mode, which is enabled only when either it is set via the register or no input
signal is present. The sampling clock in this mode is 27MHz or 54MHz. In this mode, data capture cannot
be performed in EAV (end of active video), and must be performed in SAV (start of active video) format. The
number of pixels per line is not guarantee in this mode, but data guarantee is performed in the interval from
SAV to EAV.
[7.24.4.] Auto transition mode
The AK8859VN transition function automatically switches among the above modes and selects the
optimum one, and when no input signal is present, it switches to the fixed-clock mode.
Setting for selection of clock generation mode
Name
Setting value Clock generation mode
CLKMODE0
~
CLKMODE1
[00]
Automatic
[01]
Line-locked
[10]
Frame-locked
[11]
Fixed-clock
Sub Address: 0x08 [7:6]
Notes
[7.25.] PGA (Programmable Gain Amp)
The AK8859VN digital PGA is built internally.
The digital PGA value can be set in range −4.06dB～6.90dB.
Default gain setting is 0x3C_(HEX)=0.00dB.
PGA gain equation:
Gain(dB) = 20LOG⎜⎛ ^{(2.5 × PGA) + 251.5} ⎟⎞
⎝
401.5
⎠
*PGA:PGA1orPGA2 register value_(Dec.)
At the default setting, when the composite video signal input with 0.5Vpp is input to the AIN pin, the decode
gain setting is set to appropriate range.
MS1179-E-00
AKM Confidential
- 33 -
2010/04