AK4627 Datasheet, PDF (5/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

[AK4627]
No. Pin Name
I/O Function
31 ^VCOM
O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
32 VREFH
I Positive Voltage Reference Input Pin, AVDD
33 AVDD
- Analog Power Supply Pin, 4.5V∼5.5V
34 VSS2
- Analog Ground Pin, 0V
35 DZF1
O Zero Input Detect 1 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
36 DZF2
O Zero Input Detect 2 Pin
(Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to
“H”. It always is in “L” when the PS pin is “H”.
37 RIN2-
I ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
38 RIN2+
I ADC2 Rch Analog Positive Input Pin (SGL pin = “L”)
RIN2
I ADC2 Rch Analog Input Pin (SGL pin = “H”)
39 LIN2-
I ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
40 LIN2+
ADC2 Lch Analog Positive Input Pin (SGL pin = “L”)
LIN2
I ADC2 Lch Analog Input Pin (SGL pin = “H”)
41 RIN1-
I ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
42 ^RIN1+
RIN1
I ADC1 Rch Analog Positive Input Pin (SGL pin = “L”)
I ADC1 Rch Analog Input Pin (SGL pin = “H”)
43 LIN1-
I ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
44 LIN1+
I ADC1 Lch Analog Positive Input Pin (SGL pin = “L”)
LIN1
I ADC1 Lch Analog Input Pin (SGL pin = “H”)
45 TST1
I Test Pin
This pin should be connected to VSS1.
46 SGL
I Single-ended Input Mode Select Pin.
“L”: ADC Differential Input Mode
“H”: ADC Single-ended Input Mode
47 DZFE
I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
48 SMUTE
I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
Note 1. SMUTE and DFS0 pins are ORed with register data when the PS pin= “L”.
Note 2. The output pin (DZF1 and DZF2) of zero detection results of each lineout channels can be selected by DZFM3-0
bits when the PS pin and DZFE pin= “L”. (Table 11)
Note 3. All digital input pins except for pull-down should not be left floating.
MS1278-E-02
-5-
2012/03