AK4627 Datasheet, PDF (18/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

[AK4627]
■ Audio Serial Interface Format
When TDM1 bit = “0” and TDM0 pin = “L” or when TDM1-0 bits = “00”, four modes can be selected by the DIF1-0 bits
as shown in Table 8. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1-2 are clocked out on
the falling edge of BICK and the SDTI1-3 are latched on the rising edge of BICK.
Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode TDM 1 TDM0 DIF1 DIF0 SDTO1-2 SDTI1-3
LRCK
BICK
0
0
1
0
2
0
3
0
0
0
0
24bit, Left
justified
20bit, Right
justified
H/L
I ≥ 48fs
I
0
0
1
24bit, Left
justified
24bit, Right
justified
H/L
I ≥ 48fs
I
0
1
0
24bit, Left
justified
24bit, Left
justified
H/L
I ≥ 48fs I ^(default)
0
1
1
24bit, I²S 24bit, I²S L/H I ≥ 48fs I
Table 8. Audio data formats (Normal mode)
The audio serial interface format becomes the TDM mode when the TDM0 pin is set to “H”. The serial data of all ADC
(four channels) are output from the SDTO1 pin and the SDTO2 pin outputs “L”. In the TDM256 mode, the serial data of
all DAC (six channels) are input to the SDTI1 pin. The input data to SDTI2-3 pins are ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by DIF1-0 bits as shown in
Table 9. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1 is clocked out on the falling edge
of BICK and the SDTI1 is latched on the rising edge of BICK. LOOP1-0 bits should be set to “0” at the TDM mode.
TDM128 Mode can be set by TDM1 bit as show in Table 10. In Double Speed Mode, the serial data of DAC (four
channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other two data (L3 and R3) are input to the SDTI2 pin. The TDM0
pin (or TDM0 register) should be set to “H” (or “1”) if TDM256 Mode is selected. The TDM0 register and TDM1 register
should be set to “1” if Double Speed Mode is selected in TDM128 Mode.
Mode TDM 1 TDM0 DIF1 DIF0 SDTO1
SDTI1
4
0
1
0
0
24bit, Left 20bit, Right
justified justified
5
0
1
0
1
24bit, Left 24bit, Right
justified justified
6
0
1
1
0
24bit, Left 24bit, Left
justified justified
7
0
1
1
1
24bit, I²S 24bit, I²S
LRCK
I/O
↑I
BICK
I/O
256fs I
↑ I 256fs I
↑ I 256fs I
↓ I 256fs I
Table 9. Audio data formats (TDM256 mode)
Mode
8
9
10
11
TDM 1
1
1
1
1
TDM0
1
1
1
1
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I²S
SDTI1,
SDTI2
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I²S
LRCK
I/O
↑I
BICK
I/O
128fs I
↑ I 128fs I
↑ I 128fs I
↓ I 128fs I
Table 10. Audio data formats (TDM128 mode)
MS1278-E-02
- 18 -
2012/03