AK4627 Datasheet, PDF (11/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

[AK4627]
Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 19)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb
-
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1-2 valid
(Note 20)
(Note 21)
tPD
tPDV
150
522
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK4627 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 21. These cycles are the number of LRCK rising from the PDN pin rising edge.
Note 22. I²C-bus is a trademark of NXP B.V.
max Unit
ns
ns
ns
ns
ns
ns
ns
ns
400 kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
1.0
μs
0.3
μs
-
μs
50
ns
400
pF
ns
1/fs
MS1278-E-02
- 11 -
2012/03