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AK4627 Datasheet, PDF (27/46 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC | |||
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[AK4627]
â Reset Function
(1) Reset by RSTN bit
When RSTN bit = â0â, ADC and DACs are powered-down but the internal registers are not initialized. The analog outputs
go to VCOM voltage, DZF1-2 pins output âHâ and the SDTO1-2 pins outputs âLâ. As some click noise occurs, the analog
output should be muted externally if the click noise influences system application. Figure 17 shows the power-up
sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
Normal Operation
4~5/fs (9)
1~2/fs (9)
Digital Block Power-down
516/fs (1)
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
GD (2)
Normal Operation
GD
(3)
â0âdata
â0âdata
(2)
GD
(6) (5)
(7)
Donât care
(6)
4â¼5/fs (8)
(4)
GD
Notes:
(1) The analog part of the ADC is initialized after exiting reset state.
(2) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(3) ADC outputs â0â data in power-down state.
(4) Click noise occurs when the internal RSTN bit becomes â1â. Mute the digital output externally if the click noise
influences system application.
(5) The analog outputs become VCOM voltage.
(6) Click noise occurs at 4â¼5/fs after RSTN bit becomes â0â, and occurs at 1â¼2/fs after RSTN bit becomes â1â. This
noise is output even if â0â data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in reset mode. When exiting reset mode, â1â should
be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) The DZF pins go to âHâ when the RSTN bit becomes â0â, and go to âLâ at 6~7/fs after RSTN bit becomes â1â.
(9) There is a delay, 4~5/fs from RSTN bit â0â to the internal RSTN bit â0â.
Figure 17. Reset sequence example
MS1278-E-02
- 27 -
2012/03
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