AK7738VQ Datasheet, PDF (39/42 Pages) Asahi Kasei Microsystems – Multi DSP with 5ch ADC + 4ch DAC + 8ch SRC

[AK7738]
5. I2C Interface
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
<I²C: Fast Mode>
Parameter
I²C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter
Capacitive load on bus
Symbol min typ
fSCL
-
-
tBUF
1.3
-
tHD:STA 0.6
-
tLOW
1.3
-
tHIGH
0.6
-
tSU:STA 0.6
-
tHD:DAT 0
-
tSU:DAT 0.1
-
tR
-
-
tF
-
-
tSU:STO 0.6
-
tSP
0
-
Cb
-
-
<I²C: Fast Mode Plus>
Parameter
I²C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter
Capacitive load on bus
Symbol min typ
fSCL
-
-
tBUF
0.5
-
tHD:STA 0.26
-
tLOW
0.5
-
tHIGH 0.26
-
tSU:STA 0.26
-
tHD:DAT 0
-
tSU:DAT 0.05
-
tR
-
-
tF
-
-
tSU:STO 0.26
-
tSP
0
-
Cb
-
-
max Unit
400 kHz
-
s
-
s
-
s
-
s
-
s
-
s
-
s
0.3 s
0.3 s
-
s
50 ns
400 pF
max Unit
1 MHz
-
s
-
s
-
s
-
s
-
s
-
s
-
s
0.12 s
0.12 s
-
s
50 ns
550 pF
SDA
tBUF
tLOW tR
tHIGH tF
SCL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
Figure 15. I²C-bus Interface Timing
015000122-E-00-PB
- 39 -
VIH2
VIL2
tSP
VIH2
VIL2
tSU:STO
Stop
2015/01