AK7738VQ Datasheet, PDF (37/42 Pages) Asahi Kasei Microsystems – Multi DSP with 5ch ADC + 4ch DAC + 8ch SRC

[AK7738]
4. SPI Interface
4-1. Clock Reset (CKRESETN bit = “0”)
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter
Symbol min
typ max Unit
μP Interface Signal
SCLK Frequency
(Note 51)
fSCLK
3.5 MHz
SCLK Low-level Width
tSCLKL 120
ns
SCLK High-level Width
tSCLKH 120
ns
Microcontroller → AK7738
CSN High-level Width
tWRQH 300
ns
From CSN “↑” to PDN “↑”
tRST
360
ns
From PDN “↑” to CSN “↓”
tIRRQ
1
ms
From CSN “↓” to SCLK “↓”
tWSC
300
ns
From SCLK “↑” to CSN “↑”
tSCW
480
ns
SI Latch Setup Time
tSIS
120
ns
SI Latch Hold Time
tSIH
120
ns
AK7738→ Microcontroller
Delay Time from SCLK “↓” to SO Output
tSOS
120
ns
SO Output Hold Time from SCLK “↑” (Note 49)
tSOH
120
ns
Note 49. Except when writing the 24th bit (8 bits command + 16 bits address) of the command code. This
will be the 8th bit (8 bits command) with “write preparation data read command (24H and 25H)”.
4-2. PLL Lock (CKRESETN bit = “1” and PLL is locked)
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter
Symbol min
typ max Unit
μP Interface Timing (SPI mode)
SCLK Frequency
(Note 50) (Note 51)
fSCLK
7
MHz
SCLK Low Level Width
tSCLKL 60
ns
SCLK High Level Width
tSCLKH 60
ns
μP → AK7738
CSN High Level Width
tWRQH 150
ns
From CSN “↑”to PDN “↑”
tRST
180
ns
From PDN “↑”to CSN “↓”
tIRRQ
1
ms
From CSN “↓”to SCLK “↓”
tWSC
150
ns
From SCLK “↑”to CSN “↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Hold Time
tSIH
60
ns
AK7738→ μP
Delay Time from SCLK “↓”to SO Output
tSOS
60
ns
SO Output Hold Time from SCLK “↑” (Note 49)
tSOH
60
ns
Note 50. It takes maximum 10ms to lock PLL after setting CKRESETN bit = “0”→ “1”.
Note 51. Control registers can always be accessed by a maximum speed of 7MHz. Interfacing with the
AK7738 except control registers should be made at a maximum speed of 3.5MHz when PLL is
unlocked or at a maximum speed of 7MHz when PLL is locked. It is necessary to set DLRDY bit
to “1” when interfacing with the AK7738 except control registers if PLL is unlocked.
015000122-E-00-PB
- 37 -
2015/01