AK7738VQ Datasheet, PDF (34/42 Pages) Asahi Kasei Microsystems – Multi DSP with 5ch ADC + 4ch DAC + 8ch SRC

[AK7738]
3. Serial Data Interface (SDIN1 ~ SDIN6, SDOUT1 ~ SDOUT6)
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter
Symbol min
typ
max Unit
Slave Mode
Delay Time from BICK “↑” to LRCK
(Note 46) tBLRD 10
ns
Delay Time from LRCK to BICK “↑”
(Note 46) tLRBD 10
ns
Serial Data Input Latch Setup Time
tBSIDS 10
ns
Serial Data Input Latch Hold Time
tBSIDH 5
ns
Delay Time from BICK“↓”to Serial Data Output
(Note 47)
tBSOD1
20 ns
Delay Time from BICK “↑”to Serial Data Output
(Note 46, Note 48)
tBSOD2
5
30 ns
Master Mode
BICK frequency
fBCLK
-
32, 48, 64,
128, 256
-
fs
BICK Duty cycle
50
%
Delay Time from BICK “↓” to LRCK
(Note 47)
tMBL -10
10 ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 10
ns
Delay Time from BICK“↓”to Serial Data Output
(Note 47, Note 48)
tBSOD
10 ns
Note 46. It is measured from BICK “↓” when the BICK polarity is inverted by setting BCKPx bit = “1”.
Note 47. It is measured from BICK “↑” when the BICK polarity is inverted by setting BCKPx bit = “1”.
Note 48. Set SDOPHx bit to “1” and the data should be output based on BICK “↑” when using TDM256
mode with 96kHz sampling frequency in slave mode. SDOPHx bit must be set to “0” in master
mode.
015000122-E-00-PB
- 34 -
2015/01