AK4586 Datasheet, PDF (39/54 Pages) Asahi Kasei Microsystems – MULTI CHANNEL AUDIO CODEC WITH DIR

ASAHI KASEI
[AK4586]
Mapping of Program Registers
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
Register Name
Power Down & Reset
Path Control
Clock Mode Control
Output Control
Receiver Control
I/F Format & ATT Speed
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
INT0 Mask
INT1 Mask
Receiver Status 0
Receiver Status 1
Channel Status Byte 0
Channel Status Byte 1
Channel Status Byte 2
Channel Status Byte 3
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
D7
0
0
0
0
XFS96
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
MRFS0
MRFS1
RFS96
0
C7
C15
C23
C31
PC7
PC15
PD7
PD15
D6
0
0
CLKDIV
SMUTE
AFS96
0
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
MV0
MV1
V
0
C6
C14
C22
C30
DTSCD
PC14
PD6
PD14
D5
0
LOOP1
OCKS1
TXE
CS12
ATS1
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
MSTC0
MSTC1
STC
0
C5
C13
C21
C29
PC5
PC13
PD5
PD13
D4
0
LOOP0
OCKS0
BCU
EFH1
ATS0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
MAUD0
MAUD1
AUDION
0
C4
C12
C20
C28
PC4
PC12
PD4
PD12
D3
PWVRN
IPS1
ICKS1
OVFE
EFH0
TDM
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
MDTS0
MDTS1
DTSCD
0
C3
C11
C19
C27
PC3
PC11
PD3
PD11
D2
PWADN
IPS0
ICKS0
DZFM2
DEAU
DIF2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
MAUT0
MAUT1
AUTO
PEM
C2
C10
C18
C26
PC2
PC10
PD2
PD10
D1
PWDAN
OPS1
CM1
DZFM1
DEM1
DIF1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
MPAR0
MPAR1
PAR
FS1
C1
C9
C17
C25
PC1
PC9
PD1
PD9
D0
RSTN
OPS0
CM0
DZFM0
DEM0
DIF0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
MUNL0
MUNL1
UNLOCK
FS0
C0
C8
C16
C24
PC0
PC8
PD0
PD8
Note: For addresses from 18H to 1FH, data is not written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized
to their default values.
All data can be written to the register even if PWVRN, PWADN or PWDAN bit is “0”.
MS0097-E-01
- 39 -
2001/12