AK4586 Datasheet, PDF (17/54 Pages) Asahi Kasei Microsystems – MULTI CHANNEL AUDIO CODEC WITH DIR

ASAHI KASEI
[AK4586]
OPERATION OVERVIEW
Non-PCM (AC-3, MPEG, etc.), DTS-CD Bitstream Detect
The AK4586 has the Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes to “1”. The 16bit mode Non-PCM preamble is
not detected. The AUTO bit remains “0” at that time. The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000,
0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit “1”. Once the AUTO is set to “1”, it will remain “1”
until 4096 frames pass through the chip without additional sync pattern being detected. When those preambles are
detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-10H. The AK4586 also
has the DTS-CD stream auto detect function. When the AK4586 detects the DTS-CD bitstreams, the DTSCD bit goes to
“1”. When the next sync code does not come within 4096 flames, the DTSCD bit goes to “0” until the AK4586 detects the
stream again.
Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 32kHz to 96kHz and the lock time is less than 20ms. The 96kHz detect
bit RFS96 goes to “1” when the sampling rate is 88.2kHz or more and “0” at 48kHz or less. PLL loses lock when the
received sync interval is incorrect.
Clock Operation Mode
The CM0 and CM1 bits select the clock source of MCKO and the data source of SDTO (Table 1). In mode 2, the clock
source is switched from PLL to X'tal when PLL goes to the unlock state. In mode 3, the clock source is fixed to X'tal, but
PLL is also operating and the recovered data such as C bits can be monitored.
Mode
0
1
2
3
CM1
0
0
1
1
CM0 UNLOCK PLL
X'tal Clock source
0
-
ON
OFF
PLL
1
-
OFF
ON
X'tal
0
0
ON
ON
PLL
1
ON
ON
X'tal
1
-
ON
ON
X'tal
ON: Oscillation (Power-up), OFF: STOP (Power-down)
SDTO
RX
ADC
RX
ADC
ADC
Default
System Clock
Table 1. Clock Operation Mode Select
The AK4586 has the master clock output pin, MCKO. This clock is derived from either the recovered clock or from the
crystal oscillator. In the PLL mode, the frequency of the master clock output (MCKO) is set by OCKS0 and OCKS1 bits
as shown in Table 2. 96kHz sampling is not supported at mode 2. MCKO goes to “L” when the AK4586 detect 96kHz
sampling at mode 2. Sampling speed mode is set by RFS96 or XFS96 bit (Table 3). In the x’tal mode, the x’tal frequency
rate to fs is set by ICKS1-0 bits (Table 4). In the x’tal mode, the frequency of the MCKO pin becomes half of the crystal
oscillator if the CLKDIV bit is set to “1” (Table 5). ICKS1-0 and XFS96 bits should be changed while RSTN bit is “0”. If
the external clocks are not present, the AK4586 should be in the power-down mode (PDN= “L”) or in the reset mode
(RSTN= “0”).
Mode
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO
256fs
128fs
512fs
fs
32kHz~96kHz
32kHz~96kHz
32kHz~48kHz
Reserved
Default
Table 2. Master Clock Output Frequency Select (PLL mode)
MS0097-E-01
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2001/12