AK4586 Datasheet, PDF (37/54 Pages) Asahi Kasei Microsystems – MULTI CHANNEL AUDIO CODEC WITH DIR

ASAHI KASEI
[AK4586]
(2)-2. READ Operations
Set R/W bit = “1” for the READ operation of the AK4586. After transmission of a data, the master can read next address’s
data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H
and the previous data will be overwritten.
The AK4586 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4586 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4586 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4586
discontinues transmission
S
T
S
A
R/W= “1”
T
R
O
T
P
SDA
S
Slave
Address
Data(n)
Data(n+1) Data(n+2)
Data(n+x) P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 26. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues the start
condition, slave address(R/W=“0”) and then the register address to read. After the register address’s acknowledge, the
master immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4586
generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4586 discontinues transmission.
S
S
T
T
S
A
R/W= “0”
A
R/W= “1”
T
R
R
O
T
T
P
SDA
S
Slave
Address
Sub
Address(n)
S
Slave
Address
Data(n)
Data(n+1)
Data(n+x) P
A
A
C
C
K
K
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
Figure 27. RANDOM ADDRESS READ
MS0097-E-01
- 37 -
2001/12