AK4113_1 Datasheet, PDF (37/49 Pages) Asahi Kasei Microsystems – 192KHZ 24BIT DIR WITH 6:1 SELECTOR

ASAHI KASEI
[AK4113]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
Register Name
CLK & Power Down
Control
Format & De-em Control
Input/ Output Control 0
Input/ Output Control 1
INT0 MASK
INT1 MASK
DAT Mask & DTS Detect
Receiver status 0
Receiver status 1
Receiver status 2
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
Q-subcode Address/Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
D6
CS12 BCU
V/TX DIF2
0 XTL1
EFH1 EFH0
MQIT0 MAUT0
MQIT1 MAUT1
0
0
QINT AUTO
FS3 FS2
0
0
CR7 CR6
CR15 CR14
CR23 CR22
CR31 CR30
CR39 CR38
PC7 PC6
PC15 PC14
PD7 PD6
PD15 PD14
Q9
Q8
Q17 Q16
Q25 Q24
Q33 Q32
Q41 Q40
Q49 Q48
Q57 Q56
Q65 Q64
Q73 Q72
Q81 Q80
D5
CM1
DIF1
XTL0
FAST
MCIT0
MCIT1
0
CINT
FS1
0
CR5
CR13
CR21
CR29
CR37
PC5
PC13
PD5
PD13
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
D3
CM0 OCKS1
DIF0
UCE
XMCK
MULK0
MULK1
DCNT
UNLCK
FS0
0
CR4
CR12
CR20
CR28
CR36
PC4
PC12
PD4
PD12
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
DEAU
TXE
DIV
MV0
MV1
DTS16
V
PEM
0
CR3
CR11
CR19
CR27
CR35
PC3
PC11
PD3
PD11
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
D1
D0
OCKS0 PWN RSTN
DEM1 DEM0 0
OPS2 OPS1 OPS0
IPS2 IPS1 IPS0
MSTC0 MAUD0 MPAR0
MSTC1 MAUD1 MPAR1
DTS14 MDAT1 MDAT0
STC AUDION PAR
DAT DTSCD NPCM
0
QCRC CCRC
CR2 CR1 CR0
CR10 CR9 CR8
CR18 CR17 CR16
CR26 CR25 CR24
CR34 CR33 CR32
PC2 PC1 PC0
PC10 PC9 PC8
PD2 PD1 PD0
PD10 PD9 PD8
Q4
Q3
Q2
Q12 Q11 Q10
Q20 Q19 Q18
Q28 Q27 Q26
Q36 Q35 Q34
Q44 Q43 Q42
Q52 Q51 Q50
Q60 Q59 Q58
Q68 Q67 Q66
Q76 Q75 Q74
Note: When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
For addresses from 1DH to 1FH, data must not write.
MS0349-E-02
- 37 -
2005/08