AK4113_1 Datasheet, PDF (15/49 Pages) Asahi Kasei Microsystems – 192KHZ 24BIT DIR WITH 6:1 SELECTOR

ASAHI KASEI
[AK4113]
OPERATION OVERVIEW
„ Non-PCM (Dolby Digital, MPEG, etc) and DTS-CD Bitstream Detection
The AK4113 has a non-PCM bit stream auto-detection function, When the 32bit mode non-PCM preamble based on
Dolby “Dolby Digital Data Stream in IEC 60958 Interface” is detected, the NPCM bit sets to “1”. The 96-bit sync code
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”.
Once the NPCM bit is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync
pattern being detected. When those preambles are detected, the burst preambles Pc (burst information: Table 17) and Pd
(length code: Table 18) that follow those sync codes are stored to registers. The AK4113 has also a DTS-CD bitstream
auto-detection function. When the AK4113 detects DTS-CD bitstream, the DTSCD bit sets to “1”. If the next sync code
does not occur within 4096frames, the DTSCD bit sets to “0” until a non-PCM bitstream is detected again. The ORed
value of NPCM and DTSCD bits are output to AUTO bit. The AK4113 detects the 14-bit sync word and the 16-bit sync
word of a DTS-CD bitstream, the detection function can be set ON/OFF by DTS14 and DTS16 bits in serial control
mode.
In parallel control mode, logical OR value of the AUTO and AUDION bits are outputted to the INTI pin. The DTS-CD
detects both the 14-bit sync word and the 16-bit sync word.
„ 216kHz Clock Recovery
The integrated low jitter PLL has a wide lock range from 8kHz to 216kHz. The lock time depends on sampling frequency
(fs) and FAST bit. (See Figure 12) FAST bit is useful at lower sampling frequency and is fixed to “0” in parallel control
mode. In serial control mode, the AK4113 has a sampling frequency detection function (8kHz, 11.025kHz, 16kHz
22.05kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) that uses either a clock comparison
against the X’tal oscillator or the channel status information from the setting of XTL1-0 bits. In parallel control mode, the
sampling frequency is detected by using the reference frequency, 24.576MHz. When the sampling frequency is more than
64kHz, FS96 pin goes to “H”. When the sampling frequency is less than 54kHz, FS96 pin goes to “L”. The PLL loses
lock when the received sync interval is incorrect.
FAST bit PLL Lock Time
0
≤ (15 ms + 384/fs) Default
1
≤ (15 ms + 1/fs)
Figure 12. PLL Lock Time (fs: Sampling Frequency)
MS0349-E-02
- 15 -
2005/08