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AK4113_1 Datasheet, PDF (25/49 Pages) Asahi Kasei Microsystems – 192KHZ 24BIT DIR WITH 6:1 SELECTOR | |||
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ASAHI KASEI
[AK4113]
 Error Handing
The following nine events cause the INT0 and INT1 pins to show the status of the interrupt condition. When the PLL is
OFF (Clock Operation Mode 1), INT0 and INT1 pins go to âLâ.
1. UNLCK
: PLL unlock state detect
â1â when the PLL loses lock. The AK4113 loses lock when the distance between two preamble is
not correct or when those preambles are not correct.
2. PAR
: Parity error or bi-phase coding error detection
â1â when parity error or bi-phase coding error is detected, updated every sub-frame cycle.
3. AUTO
: Non-Linear PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is available at the AUTO bit.
4. V
: Validity flag detection
â1â when validity flag is detected. Updated every sub-frame cycle.
5. AUDION : Non-audio detection
â1â when the âAUDIONâ bit in recovered channel status indicates â1â. Updated every block cycle.
6. STC
: Sampling frequency or pre-emphasis information change detection
When either FS3-0 bit or PEM bit is changed, it maintains â1â during 1 sub-frame.
7. QINT
: U-bit Sync flag
â1â when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode.
8. CINT
: Channel status sync flag
â1â when received C bit differs from the old one. Updated every block cycle.
9. DAT
: DAT Start ID detect
â1â when the category code indicates âDATâ and âDAT Start IDâ is detected. When DCNT bit is
â1â, it does not indicate â1â even if âDAT Start IDâ is detected again within â3841 x LRCKâ.
When âDAT Start IDâ is detected again after â3840 x LRCKâ passed, it indicates â1â. When
DCNT bit is â0â, it indicates â1â every âDAT Start IDâ detection.
MS0349-E-02
- 25 -
2005/08
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