AK4113_1 Datasheet, PDF (26/49 Pages) Asahi Kasei Microsystems – 192KHZ 24BIT DIR WITH 6:1 SELECTOR

ASAHI KASEI
[AK4113]
1. Parallel control mode
In parallel control mode, the INT0 pin outputs the ORed signal between UNLCK and PAR. The INT1 pin outputs the
ORed signal between AUTO and AUDION. Once INT0 goes ”H”, it maintains “H” for 1024/fs cycles after the all error
events are removed. Table 14 shows the state of each output pins when the INT0/1 pin is “H”.
UNLCK
1
0
0
x
x
x
Event
PAR AUTO
x
x
1
x
0
x
x
1
x
x
x
0
AUDION
x
x
x
x
1
0
INT0
“H”
“L”
Note 14
INT1
Note 13
“H”
“L”
Pin
SDTO
“L”
Previous Data
Output
Note 15
V
“L”
Output
Output
Note 16
Note 13. INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and AUDION.
Note 14. INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and PAR.
Note 15. SDTO pin outputs “L”, “Previous Data” or “Normal Data” in accordance with the ORed signal between
UNLCK and PAR.
Note 16. V pin outputs “L” or “Normal operation” in accordance with the ORed signal between PAR and UNCLK.
Table 14. Error Handling in parallel control mode (x: Don’t care)
2. Serial control mode
In serial control mode, the INT1 and INT0 pins output an ORed signal based on the above nine interrupt events. When
masked, the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers in 07H
and DAT bit). Once the INT0 pin goes to “H”, it remains “H” for 1024/fs (this value can be changed with the EFH1-0
bits) after all events not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are
cleared.
UNLCK, PAR, AUTO, AUDION and V bits in Address=07H indicate the interrupt status events above in real time. Once
QINT, CINT and DAT bits goes to “1”, it stays “1” until the register is read.
When the AK4113 loses lock, the channel status bit, user bit, Pc and Pd are initialized. In this initial state, INT0 pin
outputs the ORed signal between UNLCK and PAR bits. INT1 pin outputs the ORed signal between AUTO and
AUDION bits.
UNLCK
1
0
x
Event
Pin
PAR
Others
SDTO
V
x
x
“L”
“L”
1
x
Previous Data Output
x
x
Output
Output
Table 15. Error Handling in serial control mode (x: Don’t care)
TX
Output
Output
Output
MS0349-E-02
- 26 -
2005/08