AK4566 Datasheet, PDF (31/45 Pages) Asahi Kasei Microsystems – 20bit Stereo CODEC with built-in IPGA & HP-AMP

ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
03H ALC Mode Control 1
0
0
ALC ZELMN LMAT1 LMAT0 RATT LMTH
Default
0
0
0
0
0
0
0
0
LMTH: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9)
LMTH
0
1
ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 9. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC Recovery GAIN Step (Table 10)
During the ALC recovery operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 3FH, RATT = “1” is set, IPGA changes to 41H by the ALC
recovery operation, the output signal level is gained by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
RATT
GAIN STEP
0
1
Default
1
2
Table 10. ALC Recovery Gain Step Setting
LMAT1-0: ALC Limiter ATT Step (Table 11)
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by
LMTH bit, LMAT1-0 bits set the number of steps attenuated from current IPGA value. For example, when
the current IPGA value is 3FH in the state of LMAT1-0 bit = “11”, it becomes IPGA = 3BH by the ALC
limiter operation, the input signal level is attenuated by 2dB (=0.5dB x 4). When the attenuation value
exceeds IPGA = “00H” (Mute), it clips to “00H”.
LMAT1 LMAT0 ATT STEP
0
0
1
Default
0
1
2
1
0
3
1
1
4
Table 11. ALC Limiter ATT Step Setting
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (Default)
1: Disable
In case of ZELMN = “0”, when IPGA output detects zero crossing or timeout, the IPGA value is changed by
ALC operation. Zero crossing timeout is the same as ALC recovery operation. In case of ZELMN = “1”, the
IPGA value is changed immediately.
ALC: ALC Enable Flag
0: ALC Disable (Default)
1: ALC Enable
ALC is enabled at ALC bit is “1”. Default: “0” (Disable).
REV 0.5
- 31 -
2002/2