AK4566 Datasheet, PDF (22/45 Pages) Asahi Kasei Microsystems – 20bit Stereo CODEC with built-in IPGA & HP-AMP

ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
n Power-Up/Down Sequence
1) ADC
Power Supply
PDN pin
HPLMT,
HPRMT bit
PMVCM bit
Clock Input
PMADC bit
ADC Internal
State
AIN pin
SDTO pin
(1) >150ns
(2)
>0
(4)
Don’t care
Don’t care
Don’t care
(3) >0
(6) 2081/fs
(6) 2081/fs
PD(Power-down) Init Cycle Normal Operation
PD
(5)
(Hi-Z)
(7) GD
(Hi-Z)
(7) GD
Init Cycle Normal Operation
(7) GD
Figure 17. Power-up/down sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMADC bit should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate ADC. When PMADC= “0”, these clocks can be
stopped.
(5) When PMADC bit is changed to “1”, each AIN pin is biased to VCOM voltage. Rising time constant is determined by
input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1µF input capacitor, time constant
is
τ = 1µF x 12.5kΩ = 12.5ms (typ)
(6) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state. SDTO
is “L” at that time.
(7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µs@fs=44.1kHz).
REV 0.5
- 22 -
2002/2