AK4566 Datasheet, PDF (30/45 Pages) Asahi Kasei Microsystems – 20bit Stereo CODEC with built-in IPGA & HP-AMP

ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
Addr Register Name
02H Timer Select
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0
0
0
0
0
0
0
0
0
LTM1-0: ALC limiter operation period (Table 6)
When zero crossing is disabled (ZELMN = “1”), the IPGA value is changed immediately by ALC limiter
operation. When the IPGA value is changed continuously, the change is done by the period specified by
LTM1-0 bits. Default: “00”.
LTM1 LTM0
ALC Limiter Operation Period
8kHz
16kHz
44.1kHz
0
0
0.5/fs
63µs
31µs
11µs
Default
0
1
1/fs
125µs
63µs
23µs
1
0
2/fs
250µs
125µs
45µs
1
1
4/fs
500µs
250µs
91µs
Table 6. ALC Limiter Operation Period at zero crossing disable (ZELMN bit= “1”)
WTM1-0: ALC Recovery Waiting Period (Table 7)
WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during ALC
operation. Default: “00”.
WTM1
0
0
1
1
WTM0
0
1
0
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 7. ALC Recovery Operation Waiting Period
Default
ZTM1-0: ALC Zero Crossing Timeout Period (Table 8)
When IPGA output detects zero crossing or timeout, the IPGA value is changed by µP WRITE operation,
ALC recovery operation, or ALC limiter operation. Default: “00”.
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 8. Zero Crossing Timeout Period
Default
REV 0.5
- 30 -
2002/2