AK4397 Datasheet, PDF (27/37 Pages) Asahi Kasei Microsystems – High Performance Premium 32-Bit DAC

[AK4397]
■ Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4397. In parallel mode,
the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the
AK4397 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting
must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits)
and Control data (MSB first, 8bits). The AK4397 latches the data on the rising edge of CCLK, so data should be clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
Function
Parallel mode Serial mode
Auto Setting Mode
O
O
Manual Setting Mode
O
O
Audio Format
O
O
De-emphasis
O
O
SMUTE
O
O
DSD Mode
X
O
Zero Detection
X
O
Slow roll-off response
X
O
Digital Attenuator
X
O
Table 14. Function List (O: Available, X: Not available)
PDN pin = “L” resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit,
but the registers are not initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 14. Control I/F Timing
* The AK4397 does not support the read command.
* When the AK4397 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
MS0616-E-00
- 27 -
2007/05