AK4397 Datasheet, PDF (18/37 Pages) Asahi Kasei Microsystems – High Performance Premium 32-Bit DAC

[AK4397]
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK
frequency corresponding to each sampling speed should be provided (Table 9).
MCLK
Sampling Speed
1152fs
Normal (fs≤32kHz)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 8. Sampling Speed (Auto Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
N/A
N/A
N/A
16.3840 24.5760
N/A
N/A
N/A
22.5792 33.8688
N/A
N/A
N/A
24.5760 36.8640
N/A
22.5792 33.8688
N/A
N/A
N/A
24.5760 36.8640
N/A
N/A
33.8688
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
Table 9. System Clock Example (Auto Setting Mode @Serial Mode)
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
[2] DSD Mode
The external clocks, which are required to operate the AK4397, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4397 is in the normal operation mode
(PDN pin = “H”). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4397 should be reset by PDN pin = “L” after threse clocks are provided. If the
external clocks are not present, the AK4397 should be in the power-down mode (PDN pin = “L”). After exiting
reset(PDN pin = “L” → “H”) at power-up etc., the AK4397 is in the power-down mode until MCLK is input.
DCKS bit
0
1
MCLK Frequency DCLK Frequency
512fs
64fs
768fs
64fs
Table 10. System Clock (DSD Mode)
(default)
MS0616-E-00
- 18 -
2007/05