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AK2306LVM Datasheet, PDF (27/36 Pages) Asahi Kasei Microsystems – ISDN/VoIPターミナルアダプタ用 2チャンネル PCMコーデック LSI | |||
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ASAHI KASEI
[AK2306/LV]
âPCMã¤ã³ã¿ãã§ã¼ã¹ (Lomg Frame, Short Frame, GCI)
ç¹è¨ãªãå ´åãTa=-40 to +85â, VDD = 5V±5%, 3.3V±0.3V, VSS = 0V and FS 8kHzã«ããã¦ã®å®ç¾©ã¨ãªãã¾
ãããã¹ã¦ã®ã¿ã¤ãã³ã°ãã©ã¡ã¼ã¿ã¯VOH = 0.8VDDåã³VOL = 0.4Vã«ã¦æ¸¬å®ããã¾ãã
â ACç¹æ§
ãã©ã¡ã¼ã¿
è¨å· Min
FS Frequency
1/tPF ï¼
BCLK Frequency
1/tPB 128
BCLK Pulse Width High
tWBH
80
BCLK Pulse Width Low
tWBL
80
Rising Time: (BCLK,FS,DX,DR)
tR
Falling Time: (BCLK,FS,DX,DR)
tF
Hold Time: BCLK Low to FS High
tHBF
40
Setup Time: FS High to BCLK Low
tSFB
70
Setup Time: DR to BCLK Low
tSDB
40
Hold Time: BCLK Low to DR
Delay Time: BCLK High to DX valid
tHBD
40
注1ï¼ tDBD
Long Frame
Hold Time: 2nd period of BCLK Low to FS Low
tHBFL
40
Delay Time: FS or BCLK High, whichever is later,to DX valid
注1ï¼ tDZFL
Delay Time: BCLK Low to DX High-Z
注1ï¼
tDZCL
10
FS Pulse Width Low
tWFSL
1
Short Frame
Hold Time: BCLK Low to FS Low
Setup Time: FS Low to BCLK Low
Delay Time: BCLK Low to DX High-Z
GCI
tHBFS
40
tSFBS
40
注1ï¼ tDZCS 10
BCLK Frequency
Delay Time: Second BCLK Low to DX High-Z
Setup Time: DR to Second BCLK High
Hold Time: Second BCLK High to DR
注ï¼ï¼15pFã®è² è·å®¹éåã³ï¼ã¤ã®LSTTLé§åæã
1/tPBG 512
tDZCG
10
tSDBG
40
tHBDG
40
Typ Max åä½ åç
§å³
8
ï¼ kHz
4096 kHz
ns
ns
40
ns å³ï¼
40 ns å³ï¼
å³ï¼
ns
ns
ns
ns
60 ns
ns
60 ns
å³ï¼
60 ns
BCLK
ns
ns å³ï¼
60 ns
4096 kHz
60 ns
å³ï¼
ns
ns
MS0093-J-06
27
2012/01
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