AK4533 Datasheet, PDF (25/40 Pages) Asahi Kasei Microsystems – Audio Codec with Touch Screen Controller

[ASAHI KASEI]
MCLK Control
Master Clock frequency for audio codec is input to MCLK pin.
If sampling frequency is equal to or less than 22.05kHz, MSEL bit should be set to "0", requiring 512fs clock as MCLK pin. If
sampling frequency is more than 22.05kHz, MSEL bit should be "1", requiring 256fs clock as MCLK pin. When MSEL bit is changed,
MSEL bit must be written with all "1" of ADPD bit, DALPD bit and DARPD bit (power-down state). In addition to this, master clock,
MCLK should be stopped.
MSEL: Selection of 256/512fs
“0”: 512fs Default
“1”: 256fs
Power-down Control
ADPD, DALPD, and DARPD can control power-down state of ADC and DAC. The AK4533 can power down Left channel of DAC
and Right channel DAC independently.
ADPD:
A/D Converter Power-down Enable
(0: Disable 1: Enable)
The write "1" to ADPD bit enables IPGA block and ADC to power down, and 00h - 03h registers are reset to default value.
The AK4533 ignores the write operation to 00h -03h registers.
The read operation is possible (The AK4533 outputs default value)
The write "0" to ADPD bit enables normal operation of ADC block.
The period (516Ts@ MSEL="1", 260Ts@ MSEL="0" is required until VREFAD is stable. The write to the registers is
possible in this initial period, but AGC function is disabled for this period. The AK4533 initiates AGC operation
automatically after the end of the period.
DALPD: Left Channel D/A Converter Power-down Enable
(0: Disable 1: Enable)
The write "1" to DALPD bit enables Left Channel D/A converter to power down. DALPD bit is set to "0", Left Channel of
D/A converter goes to normal state.
DARPD: Right Channel D/A Converter Power-down Enable
(0: Disable 1: Enable)
The write "1" to DARPD bit enables Right Channel D/A converter to power down. DARPD bit is set to "0", Right Channel
of D/A converter goes to normal state.
<Revision 0.9a>
24
July 00