AK4533 Datasheet, PDF (21/40 Pages) Asahi Kasei Microsystems – Audio Codec with Touch Screen Controller

[ASAHI KASEI]
„ Overview of AGC operation
The AK4533 detects and compares the analog input level of ADC per 64fs. The AK4533 has three zones for AGC operation; Limit
Zone, Recovery Zone, and Insensitive Zone. At first, AGC circuit detects the zone in which the signal level is, and detects how long the
signal is in that zone.
If the signal level enters in Limit Zone that is specified by TH0 bit and TH1 bit, AGC automatically decreases IPGA value per the step
that is specified by LSTEP0 bit and LSTEP1 bit to suppress the signal.
If the signal is in Recovery Zone in the period that is called as "Recovery Time", AGC automatically increases IPGA value per the step
that is specified by RSTEP0 bit and RSTEP1 bi to amplify the signal. Recovery Time is specified by RWT0 bit, RWT1 bit and MSEL
bit.
If the signal level is in Insensitive Zone, which is named for the area between Limit Zone and Recovery Zone, AGC does nothing, and
Recovery Counter is cleared.
Reference level of Limit Zone and Recovery Zone can be changed by the combination of TH0 bit and TH1 bit as Table 3.
Addr = 00h TH1-0: AGC Level
TH1 TH0 The Range of Limit Zone
0 0 ADC_INPUT ≥-8.0dBFS
0 1 ADC_INPUT ≥-6.0dBFS
1 0 ADC_INPUT ≥-4.0dBFS
default 1 1 ADC_INPUT ≥-2.0dBFS
The Range of Recovery Zone
ADC_INPUT ≤ -10.0dBFS
ADC_INPUT ≤ -8.0dBFS
ADC_INPUT ≤ -6.0dBFS
ADC_INPUT ≤ -4.0dBFS
Table 3. Setting of Limit/Recovery Zone
Senseless Zone
-8.0dBFS > ADC_INPUT > -10.0dBFS
-6.0dBFS > ADC_INPUT > -8dBFS
-4.0dBFS > ADC_INPUT > -6dBFS
-2.0dBFS > ADC_INPUT > -4.0dBFS
„Limit Operation
When signal enters Limit Zone, IPGA value is actually updated when the signal crosses the signal ground. As the special case, if the
signal doesn't cross the ground within the timeout period that is specified by the Table 4 although the input signal entered Limit Zone
once, the AK4533 forces to decrease IPGA value after the specified timeout passes.
MSEL
Zero-Cross Timeout
“L”
60Ts
8kHz
11.025kHz
22.05kHz
44.1kHz
7.5ms
5.4ms
2.7ms
NA
“H”
124Ts
8kHz
11.025kHz
22.05kHz
44.1kHz
NA
NA
NA
2.8ms
Table 4. Zero-Cross Timeout Table for Limit Operation.
Addr = 01h LSTEP1-0: ATT Step at Limit Operation
LSTEP0 bit and LSTEP1 bit specify the decrement step size of IPGA value at Limit operation. For example, if the current value of
IPGA is 0x46, and if LSTEP0 and LSTEP1 are "11", IPGA is updated to 0x42.
default
LSTEP1
0
0
1
1
LSTEP0
0
1
0
1
ATT STEP
0.5dB
1.0dB
1.5dB
2.0dB
<Revision 0.9a>
20
July 00