AK4533 Datasheet, PDF (24/40 Pages) Asahi Kasei Microsystems – Audio Codec with Touch Screen Controller

[ASAHI KASEI]
Addr = 04h Mute Mute Control
When the Mute bit is set to "1", input data to D/A converter is forced to set to zero regardless of D/A data from SDI pin. When the
Mute bit is set to "0", D/A data is enabled. When reset, default value of Mute bit is "0".
Addr = 04h M3-0: Digital ATT Output Control
These bits control the attenuation level of DAC output. Step size of ATT is approximately 1.5dB. This value is still preserved even if
DALPD bit and/or DARPD bit are set and/or reset.
default
DATA (HEX)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
DATT (dB)
0
1.48
2.95
4.43
6.02
7.5
8.97
10.45
12.04
13.52
14.99
16.47
18.06
19.54
21.01
22.49
STEP
1.5dB
Figure 13 describes the recovery operation.
Limit
Operation
Recovery Operation Cycle
Recovery Operation
Inhibited State
Recovery Operation Cycle
Recovery
Ready
Recovery Operation
Inhibited State
Recovery Operation Cycle
Timeout
Recovery
Ready
Recovery
Inhibited
Recovery
Ready
Zero-Cross
IPGA
Ready t Update
IPGA value
IPGA=2F
IPGA=30
IPGA=31
Figure 13. The Flow of Recovery Operation
<Revision 0.9a>
23
July 00