AK4533 Datasheet, PDF (18/40 Pages) Asahi Kasei Microsystems – Audio Codec with Touch Screen Controller

[ASAHI KASEI]
(a) Audio Streaming I/F (AS I/F)
Audio data is transported by the control of 5-wire; MCLK, SCLK, LRCK, SDO, and SDI.
256fs or 512fs clock is input to MCLK pin as master clock for audio codec. The write the appropriate value to MSEL bit in the register
0h through A/T I/F is needed before master clock is input to the device. If the sampling frequency (fs) is equal to or less than 22.05kHz,
MSEL bit should be set to "0", which selects 512fs mode to suppress out-band noise. If fs is more than 22.05kHz, MSEL bit must be set
to "1", which select 256fs mode.
Note that MSEL bit should be set under power-down state (ADPD = "1", DALPD="1", DARPD="1")
Bit clock is 32fs that is synchronized to master clock, and is output via SCLK pin. Audio frame signal is also output via LRCK pin, and
its frequency is fs. The device keeps LRCK signal high level for 1/2fs period in which left channel data is input to or output from the
device, and keeps LRCK signal low level for 1/2fs period in which right channel data is input to the device. If at least one of ADPD bit,
DALPD bit, or DARPD bit is "0", LRCK signal and SCLK signal are output from the device. If all of the above bits are "1", SCLK and
LRCK are fixed to "L" level.
A/D data is 1 channel, and is output via SDO pin while LRCK is "H". A/D data format is 2's complement, 16 bit, and MSB first. SDO
is "L" while LRCK is "L". As A/D data is output at the falling edge of SCLK, A/D data should be latched at the rising edge of SCLK.
Left channel D/A data and right channel D/A data should be input in the first half of Ts and in the second half of Ts respectively. The
device latches D/A data at the rising edge of SCLK, D/A data must be input to SDI pin at the falling edge of SCLK. D/A data format is
2's complement, 16 bit, and MSB first.
1/32fs period
Frame Period (Ts=1/fs)
SLCK(o)
LRCK(o)
SDO (o)
D15 D14
SDI(i) ^{D1 D0 D15 D14}
ADC Data
D2 D1 D0
D2 D1 D0 D15 D14
D2 D1 D0
Lch DAC Data
Rch DAC Data
Figure 11. Audio Streaming Data Timing
Table 1 shows the relationship between Sampling frequency (fs) and master clock frequency.
Sampling Frequency (fs)
MSEL bit
MCLK
SCLK (32fs)
LRCK (1fs)
44.1kHz
“1”(256fs mode)
11.2896MHz
1.4112MHz
44.1kHz
22.05kHz
“0”(512fs mode)
11.2896MHz
705.6kHz
22.05kHz
11.025kHz
“0”(512fs mode)
5.6448MHz
352.8kHz
11.025kHz
8.0kHz
“0”(512fs mode)
4.096MHz
256kHz
8.0kHz
Table 1. The relationship between sampling frequency and master clock frequency
<Revision 0.9a>
17
July 00