AK4126 Datasheet, PDF (23/27 Pages) Asahi Kasei Microsystems – 6ch 192kHz / 24-Bit Asynchronous SRC

ASAHI KASEI
[AK4126]
1. Grounding and Power Supply Decoupling
The AK4126 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical. AVSS and DVSS must be connected to the same
ground plane. Decoupling capacitors should be as near to the AK4126 as possible, with the small value ceramic
capacitor being the nearest.
2. Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4126. The jitter frequency and the jitter amplitude shown
in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4126 operate normally
regardless of the jitter frequency.
10.00
AK41256 Jitteerr TToolelerraannccee
1.00
0.10
(2)
0.01
0.00
1
10
(3)
(1)
100
Jitter Frequency [Hz]
1000
10000
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/L/L”, “L/L/H”, “L/H/L”, the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one
cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8µs.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 17. Jitter Tolerance
MS0544-E-00
- 23 -
2006/09