AK4126 Datasheet, PDF (21/27 Pages) Asahi Kasei Microsystems – 6ch 192kHz / 24-Bit Asynchronous SRC

ASAHI KASEI
[AK4126]
„ PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. (See Figure 15,
Table 8 and Table 9) Please be careful the noise onto the FILT pin. When using IBICK, the value of an external element
doesn't depend on the IBICK input frequency.
AK4126
FILT
R
C2
C1
AVSS
Figure 15. PLL Loop Filter
1. When using ILRCK
PLL2
L
L
L
PLL1
L
L
H
PLL0
ILRCK
R [Ω]
C1 [µF]
L
8k ∼ 96kHz
1.8k ± 5%
0.68 ± 30%
H
8k ∼ 192kHz
16k ∼ 192kHz
1k ± 5%
1.5k ± 5%
1.0 ± 30%
0.68 ± 30%
L
8k ∼ 192kHz
16k ∼ 192kHz
1k ± 5%
1.5k ± 5%
1.0 ± 30%
0.68 ± 30%
Table 8. PLL Loop Filter (ILRCK Mode)
C2 [nF]
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 192kHz.
- Note. Tolerance of R, C1, and C2 includes the temperature characteristics.
2. When using IBICK
PLL2
H
PLL1
x
PLL0
ILRCK
R [Ω]
C1 [µF]
x
8k ∼ 192kHz 470 ± 5%
0.22 ± 30%
Table 9. PLL Loop Filter (IBICK Mode, “x”: Don’t care)
- Note. The IBCIK must be continuous except when the clocks are changed.
- Note. IBCIK = 32fsi is supported only 16bit LSB justified and I²S Compatible.
- Note. Tolerance of R, C1, and C2 includes the temperature characteristics.
C2 [nF]
1.0 ± 30%
MS0544-E-00
- 21 -
2006/09