AK4126 Datasheet, PDF (20/27 Pages) Asahi Kasei Microsystems – 6ch 192kHz / 24-Bit Asynchronous SRC

ASAHI KASEI
[AK4126]
„ Internal Reset Function for Clock Change
The change of the clock supplied to the AK4126 is shown in Figure 14. SDTO shows SDTO1, SDTO2 and SDTO3.
External clocks
(Input port
or Output port)
Clocks 1
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state)
Normal operation Power-down
PLL lock &
fs detection
Normal operation
SDTO
Normal data
Note1
Normal data
SMUTE (Note2,
(1)
recommended)
(1)
0dB
Att.Level
-∞dB
(1) Soft mute cycle. (See Table 6)
E.g. SMT1 pin = “L”, SMT0 pin = “L”, fso = 48kHz
Soft mute cycle: 1024/fso = 21.3ms
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
“L”, which will cause the data on SDTO to remain “0”.
Note 2. SMUTE can also be used to remove the unknown data.
Figure 14. Sequence of changing clocks
„ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0544-E-00
- 20 -
2006/09