AK4126 Datasheet, PDF (13/27 Pages) Asahi Kasei Microsystems – 6ch 192kHz / 24-Bit Asynchronous SRC

ASAHI KASEI
[AK4126]
OPERATION OVERVIEW
„ System Clock & Audio Interface Format for Input PORT
The input port works in slave mode. The clocks supply ILRCK and IBICK externally. An internal system clock is created
by the internal PLL using ILRCK (Mode 0 ∼ 2 of Table 2) or IBICK (Mode 4, 5, 7of Table 2). The PLL2-0 pins and
IDIF2-0 pins select the PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when PDN pin = “L”.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s complement format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when PDN pin = “L”. The audio
interface format of SDTI1, SDTI2 and SDTI3 becomes the same setting. The maximum input frequency of IBICK is 64fsi.
Mode
0
1
2
3
4
5
6
7
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
IDIF0
L
H
L
H
L
H
L
H
SDTI Format
IBICK Frequency
16bit, LSB justified
≥ 32fsi
20bit, LSB justified
≥ 40fsi
24/20bit, MSB justified
≥ 48fsi
24/16bit, I²S Compatible ≥ 48fsi or 32fsi
24bit, LSB justified
≥ 48fsi
Reserved
Reserved
Reserved
Table 1. Input Audio Interface Format (Input PORT)
Mode
0
1
2
3
4
5
6
7
PLL2
L
L
L
L
H
H
H
H
PLL1
L
L
H
H
L
L
H
H
PLL0
L
H
L
H
L
H
L
H
ILRCK Freq IBICK Freq
8k ∼ 96kHz
8k ∼ 192kHz
16k ∼ 192kHz
(Note 11)
8k ∼ 192kHz
(Note 12)
8k ∼ 192kHz
(Note 12)
Depending on
IDIF2-0
(Note 12)
Reserved
32fsi (Note 13)
64fsi
Reserved
64fsi
SMUTE
(Note 14)
Manual
Semi-Auto
Manual
Semi-Auto
Note 11. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 12. The IBCIK must be continuous except when the clocks are changed.
Note 13. IBCIK = 32fsi is supported only 16bit LSB justified and I²S Compatible.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
Table 2. PLL Setting (Input PORT)
MS0544-E-00
- 13 -
2006/09