AK4126 Datasheet, PDF (22/27 Pages) Asahi Kasei Microsystems – 6ch 192kHz / 24-Bit Asynchronous SRC

ASAHI KASEI
[AK4126]
SYSTEM DESIGN
Figure 16 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
• Input PORT: Slave mode, IBICK lock mode (64fsi), 24 bit MSB justified
• Output PORT: Slave mode, 24 bit MSB justified
• Dither = OFF, De-emphasis = OFF, PM = 6ch mode
C1: 0.1µ
C2: 10µ
3.3V
+
C2
C1
0.22µ
1n
+
C2
C1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DSP1
fsi
64fsi
C1
1 NC
2 TEST0
3 ILRCK
4 IBICK
5 DVDD
6 DVSS
7 TST0
8 SDTI1
9 SDTI2
10 SDTI3
11 IDIF0
12 IDIF1
13 IDIF2
14 TST1
15 TST2
16 NC
Top View
NC 48
TEST4 47
OLRCK 46
OBICK 45
DVDD 44
fso
64fso
C1
DVSS 43
TST6 42
SDTO1 41
SDTO2 40
SDTO3 39
ODIF0 38
ODIF1 37
TEST3 36
TEST2 35
TEST1 34
NC 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C1
+
C2
DSP2
uP
Notes:
- All digital input pins should be not left floating.
- AVSS and DVSS must be connected to the same ground plane.
Figure 16. Typical Connection Diagram
MS0544-E-00
- 22 -
2006/09