AME9002 Datasheet, PDF (22/37 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9002
Preliminary
CCFL Backlight Controller
In order to enable the first two fault condition checks
then the OVP pin must, indirectly, sense the high volt-
age at the input of the CCFL. The actual CCFL voltage
must be reduced by using either a resistor or capacitor
divider such that in normal operation the voltage at OVPL
is lower than 2.5V and the voltage at OVPH is lower than
3.3V.
The third fault condition check can be used to monitor
the CCFL current. Specifically, it checks whether the
voltage at the CSDET pin is higher than 1.25V. If CSDET
does not cross its 1.25V threshold once during 4 suc-
cessive clock cycles then this fault will be triggered. This
protection is disabled while the SSC ramp is below 3V,
such as at the beginning of every dimming cycle. This
fault check is disabled during the start up mode, as are
all the fault checks. This fault condition is used to check
that a reasonable minimum amount of current is flowing
in the tube.
Figure 17 is a simplified schematic of the fault protec-
tion circuitry used in the AME9002. Most of the signals
have been previously defined however some need a little
explanation. The VDDOK signal is a power OK signal
that goes high when the 5V supply (VDD) is valid. The
CHOP signal stops the operation of the switching cir-
cuitry once every dimming cycle for burst mode bright-
ness control. The output signal, FIRST, is high during
the start up mode then is low during subsequent cycles.
It causes the SSC pin to initially source 1000 times less
current than on subsequent dimming cycles in order to
provide the 1 second initial start up period. The NORM
signal is an enable signal to the switching circuitry. When
it is high the circuit works normally. When it is low the
switching circuitry stops.
SSC and SSV pins
Besides defining the initial 1 second start up period
the SSC pin’s primary role is to define a time period in
which the 2nd and 3rd fault condition (previously de-
scribed) are disabled. This period of time is called the
blanking interval. During the initial start up period after a
power on reset or just after a low to high transition on the
CE pin the SSC pin sources 140nA into an external ca-
pacitor, C3. For subsequent dimming cycles the SSC
pin sources 140uA. During steady state operation the
blanking interval is defined as the time during which
V(SSC) < 3V. Once the voltage at SSC crosses 3V the
blanking interval is finished and all three fault condition
checks are enabled. (The OVPH > 3.3V fault check is
always enabled after the initial start up period.) At the
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beginning of the next dimming cycle the SSC pin is pulled
to VSS then allowed to ramp upwards again.
During steady state operation the SSV pin (like the
SSC pin) is pulled to ground at the beginning of every
dimming cycle then sources 20uA into an external ca-
pacitor. This creates a 0 to 5 volt ramp at the SSV pin.
This ramp is used to limit the duty cycle of the PWM
gate drive signal available at the OUTA pin. The SSV pin
accomplishes duty cycle limiting by clamping the COMP
voltage to no higher than the SSV voltage. Because the
magnitude of the COMP voltage is proportional to the
duty cycle of the PWM signal at OUTA the duty cycle
starts each dimming cycle at zero and slowly increases
to its steady state value as the voltage at SSV increases.
(Figure 9 shows this operation.)
During the initial start up mode the SSV pin starts at
zero volts and ramps up to 5V just as in steady state
operation. However, during the start up mode, if OVPH >
3.3V then SSV is pulled to VSS and only allowed to ramp
up when OVPH < 3.3V. This action sets the duty cycle
back to 0 volts then allows the duty cycle to increase as
the SSV voltage increases.
This type of duty cycle limiting is commonly called
“soft-start” operation. Soft start operation lessens over-
shoot on start up because the power increases gradually
rather than immediately.
Unlike the SSC pin the current sourced by the SSV pin
remains approximately 20uA during ALL dimming cycles.
BATTFB
The BATTFB pin is designed to sense the battery volt-
age and enable the pin OUTA. When the voltage at
BATTFB is below 1.25 volts then OUTA is disabled, when
the voltage at BATTFB is larger than 1.5V then OUTA is
enabled. There is 250mV of hysteresis between the turn
on and the turnoff thresholds. This pin does not disable
any other portion of the circuit except the OUTA pin.
Notably, the other two drivers, OUTAPB and OUTC con-
tinue to switch when the voltage at BATTFB is below
1.25V.
Ringing
Due to the leakage inductances of transformer T1 volt-
ages at the drains of Q3 can potentially ring to values
substantially higher than the ideal value (which is twice
the battery voltage). The application schematic in Figure
17 uses a snubbing circuit to limit the extent of the ring-
ing voltage. Components C9,R8,D2 and D3 make up the