AME9002 Datasheet, PDF (21/37 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9002
Preliminary
CCFL Backlight Controller
RT2, RDELTA pin
The frequency of the drive signal at the gate of Q2 is
determined by the VCO shown in Figure1. A detail of the
VCO is shown in Figure 14. The user sets the minimum
oscillator frequency with the resistor connected to pin
RT2 (R2 in the figures). The relation is:
Frequency (Hz) = 2.8E9 / R2 (ohms)
You can see from the formula that as R2 is increased
the frequency gets smaller.
Resistor R3 controls how much the oscillator frequency
increases as a function of the voltage at FCOMP. The
relationship is:
Delta frequency (Hz) = 3.44E8 * (5 - V(FCOMP)) / R3
You can see from the formula that the frequency will
decrease as the FCOMP voltage increases. The amount
of this increase is set by R3. The current in R3 decreases
as the voltage at FCOMP increases and hence decreases
the charging current into the timing capacitor of Figure
14 thereby decreasing the oscillator frequency.
Supply voltage pins, VDD and PNP
Most of the circuitry of the AME9002 works at 5V with
the exception of one output driver. That driver (OUTA)
and its power pad (VBATT) must operate up to 24V al-
though the OUTA pad may never be forced lower than 8
volts away from the VBATT pin. The OUTA pin is inter-
nally clamped to approximately 7.5 volts below the Vbatt
pin.
The AME9002 uses an external PNP device to provide
a regulated 5V supply from the battery voltage (See Fig-
ure 15). The battery voltage can range from 7V< VBATT <
24V. The PNP pin drives the base of the external PNP
device, Q1. The VDD pin is the 5V supply into the chip.
A 4.7uF capacitor, C7, bypasses the 5V supply to ground.
If an external 5V supply is available then the external
PNP would not be necessary and the PNP pin should
float.
When the CE pin is low (<0.4V) the chip goes into a
zero current state. The chip puts the PNP pin into a high
impedance state which shuts off Q1 and lets the 5V sup-
ply collapse to zero volts. When low, the CE pin also
immediately turns PMOS transistor Q2 off, however tran-
sistors Q3-1 and Q3-2 will continue to switch until the 5V
has collapsed to 3.5V. By allowing the Q3 transistors to
continue to switch for some time after Q2 is turned off
the energy in the tank circuit is dissipated gradually with-
out any large voltage spikes.
The VDD voltage is sensed internally so that the switch-
ing circuitry will not turn on unless the VDD voltage is
larger than 4.5V and the internal reference is valid. Once
the 4.5V threshold has been reached the switching cir-
cuitry will run until VDD is less than 3.5V (as mentioned
before).
Output drivers (OUTA, OUTAPB, OUTC)
The OUTAPB and OUTC pins are standard 5V CMOS
driver outputs (with some added circuitry to prevent shoot
through current). The OUTA driver is quite different (See
Figure 16). The OUTA driver pulls up to VBATT (max
24V) and pulls down to about 7.5 volts below VBATT. It is
internally clamped to within 7.5V of VBATT. On each
transition the OUTA pad will sink/source about 500mA for
100nS. After the initial 100ns burst of current the current
is scaled back to 1mA(sinking) and 12mA(sourcing). This
technique allows for fast edge transitions yet low overall
power dissipation.
Fault Protection, the OVPH, OVPL and CSDET pins
During the startup mode the AME9002 does not actu-
ally sense for fault conditions, instead it uses the volt-
ages at OVPL and OVPH to adjust the operating fre-
quency for a smooth start up. The startup itself (or
“strike”) is detected when the voltage at CSDET rises
above 1.25V. There are no voltages at OVPL, OVPH or
CSDET that can cause a fault during the start up mode.
During steady state operation the AME9002 checks
for 3 different fault conditions. There are two overvoltage
conditions and one undercurrent condition that can cause
a fault. When any one of the fault conditions is met then
the circuit is latched off. Only a power on reset or tog-
gling the CE pin will restore the circuit to normal opera-
tion. (See Figure 17 for a schematic of the FAULT cir-
cuitry.)
The first fault condition check can be used to detect
overvoltages at the CCFL. Specifically, if the OVPH pin
is above 3V then this fault condition is detected. The
first fault condition is always enabled, there is no blank-
ing period (except, of course, during the start up period
when fault detection is disabled).
The second fault condition checks that the voltage at
OVPL is below 2.5V. This protection is disabled while
the SSC ramp is below 3V such as during the beginning
of every dimming cycle. Again, this check is disabled
during the start up period like all the fault checks.
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