AME9002 Datasheet, PDF (2/37 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9002
Preliminary
CCFL Backlight Controller
n Pin Description
Pin #
1
2
3
4
Pin Name
VREF
CE
SSC
RDELTA
Pin Description
Reference. Com pensation point for the 3.4V internal voltage reference. Mus t have
bypass capacitor connected here to VSS.
Chip enable. When low (<0.4V) the chip is put into a low current (~0uA) shutdown
mode.
Blanking interval ramp. During the first cycle this pin sources 140nA. The first cycle
is used to define the initial start up period, often on the order of one second. During
s ubs equent cycles SSC s ources 140mA. This is prim arily us ed to provide a "blanking
interval" at the beginning of every dimming cycle to temporarily disable the fault
protection circuitry. The blanking interval is active when V(SSC) < 3.0 volts. (See
application notes.)
A res is tor connected from this pin to VDD determines the am ount that the voltage at
FCOMP modulates the switching frequency. The frequency is invers ely proportional to
the voltage at FCOMP.
5
FAULTB
FAULTB pulls low when a fault is detected.
6
RT2
A res is tor from this pin to VSS sets the minim um frequency of the VCO. The voltage at
this pin is 1.5V
7
VSS
Negative supply. Connect to system ground.
Over voltage protection input (HIGH). Indirectly senses the voltage at the secondary of
the transformer through a resistor (or capacitor) divider. During the initial start up
8
OVPH
period, if OVPH is > 3.3V, FCOMP is driven towards VSS (increasing the frequency)
and SSV is res et to zero (which decreas es the duty cycle). After the initial s tart up
period is completed the circuit will shut down if OVPH is > 3.3V.
Over voltage protection input (LOW). During the initial start up period if OVPL < 2.5
volts then FCOMP is allowed to ramp up (decreasing the os cillator frequency allowing
9
OVPL
the circuit to get closer to resonance). If, during the initial start up period, OVPL > 2.5
volts then FCOMP is held at its original value (not allowed to increase so the
oscillator frequency stays constant). This action is des igned to hold the voltage
across the CCFL constant while the CCFL "warms up".
Frequency control point. Initially this pin is at VSS which yields a m axim um switching
frequency. Depending on the voltage at OVPL and OVPH the pin FCOMP will normally
10
FCOMP
ramp upwards lowering the switching frequency towards the circuit’s res onant
frequency.
2